The present invention pertains to the field of closed loop systems and apparatus for inhibiting such systems from being erroneously locked up in response to temporary malfunctions of components within the loop.
Phase locked loop (PLL) systems for tuning a television receiver have recently found acceptance with television receiver manufacturers because they are capable of generating local oscillator signals having relatively accurate and stable frequencies. In addition, the frequencies of the local oscillator signals are readily programmable in response to binary signals representing channel numbers. Generally, PLL tuning systems include a reference oscillator, a reference divider for dividing the frequency of the output signal of the reference oscillator, a prescaler for dividing the frequency of the local oscillator output signal by a predetermined factor, a programmable divider for dividing the frequency of the output signal of the prescaler by a factor determined by the presently selected channel, a phase comparator for generating a series of pulses representing the phase and/or frequency deviation between the output signal of the reference divider and the output signal of the programmable divider and a low pass filter for deriving a control voltage for the local oscillator in response to the pulses generated by the phase comparator.
Unfortunately, PLL systems, because of their closed loop configurations, may become erroneously locked up in a condition corresponding to either one of the two extremes of the control voltage generated by the low pass filter due to a temporary malfunction of one of the components of the loop. For example, the control voltage may be driven to and held at one of its two extremes when amplitude of the local oscillator signal is below the counting threshold of the prescaler. In such a case the prescaler will not properly count and may, in fact, self-oscillate and thus mask the true frequency of the local oscillator signal.
While malfunction detectors for closed loop systems which detect and attempt to correct for temporary malfunctions of components within the loop are known (see, for example, U.S. Pat. No. 3,971,991--Tanaka), these detectors are not particularly well suited to PLL systems and not capable of correcting for all the possible erroneously locked up, hereinafter referred to as "hangup", conditions encountered in such systems.